Horace Hub · the bottom of the chain
Why a flip makes heat: following the electrons
Your note of Mon 26 Oct asked why a transistor flip releases heat, and to see the electrons move. In short: every flip charges or drains a tiny capacitor through a transistor, and the carriers crossing that transistor hand their energy to the silicon lattice. Each flip leaves ½CV² of heat, whatever the transistor.
1The supply pays CV²; half is heat at once, half on the way down
Charging a node: the supply pays the whole square, the node keeps only the lower triangle
Your open netlist's average toggling net, C = 2.233 fF, charged to 0.517 V.
A gate's output is a node with a small capacitance: the next gates' inputs plus the wire. Raising it from 0 to V takes charge Q = CV, and every bit of that charge leaves the supply at the full V, so the supply pays QV = CV². The node keeps only ½CV², because the first charge went on while it was still near 0 V. The other half is lost in the pull-up transistor on the way. When the node falls, its stored ½CV² drains to ground through the pull-down and becomes heat too. So every flip, up or down, leaves ½CV². The split doesn't depend on the transistor: a weaker one charges the node more slowly and loses exactly the same.
Where it turns into heat: the field across the conducting channel speeds the carriers up, and they give that energy to the silicon lattice by scattering off it, setting the lattice vibrating (phonons). That's Joule heating. In a 7 nm transistor the channel is so short that many carriers cross it with few collisions and shed most of their energy at the drain end, mostly as optical phonons, which barely move and decay into the acoustic phonons that carry heat away (Pop, Sinha and Goodson, 2006). The wire's resistance takes its share too, in proportion to its share of the resistance on the path.
2The inverter, electron by electron
New to electronics? Section 7, the inverter in depth, starts from zero: the inverter's history, the five ideas of electricity you need, the transistor as a switch, and twelve step-by-step demos. Then come back here.
Each edge moves 7,206 electrons and leaves 0.298 fJ of heat; only the rise draws from the supply
A CMOS inverter at 0.517 V driving your open netlist's average net. Each dot is a packet of about 300 electrons.
The circuit
The same edge as electron energy
For an electron, ground is uphill of the rail. The node's level slides down as it charges. Early electrons fall far, late ones barely: on average half the 0.517 eV, so ½CV² per edge.
The output is low. Press “Input 1→0” to raise it, or Play to watch both edges.
When the input falls, the p-type transistor (PMOS) conducts and the output rises. Electrons leave the node's top plate, cross to the VDD rail and enter the supply, which lifts each one by 0.517 eV and pushes one out at ground, into the capacitor's bottom plate. When the input rises, the n-type transistor (NMOS) conducts and the output falls: electrons come up from ground through the NMOS and refill the top plate. Over a full cycle electrons go ground → node → rail, the opposite way to the current arrows, as your 26 Oct fix says.
Inside the PMOS the current is carried by holes, the gaps where electrons are missing, so there the hollow dots move down: the same current, as valence electrons hop up into the gaps. All the dots move together because a series loop carries one current. Real electrons drift slowly; what travels fast is the push, the way a full pipe delivers water at the far end the moment you push at the near end.
3What else heats it: three smaller sources ride on top
At 0.517 V the load's CV² is 92.6% of an inverter's switch; the inverter's own share is 7.4%
One INVx1 driving a 2.105 fF net, ASAP7 in SPICE at 0.517 V, per cycle (rise plus fall): 0.6077 fJ.
Short circuit
While the input ramps, both transistors are briefly half on and current runs straight from rail to ground. At the edges this design makes (23 ps rising, 17 ps falling), short circuit and gate-to-drain (Miller) coupling together add 1.3–3.0% to a switch. A slow 2 ns edge adds 7.5% at 0.517 V and 59% at 0.7 V.
Leakage
An off transistor still passes a trickle, switching or not, and it grows with temperature. One SPICE inverter leaks 0.035–0.043 nA at 0.517 V and 25 °C. For the card, your idle law is 12.6 W fixed plus a leakage term of 23.3 W at 80 °C that e-folds every 36 °C; E66 is measuring the two terms apart on aifoundry2 this morning.
Glitches
When a gate's inputs arrive at different times, its output can flip and flip back before it settles, and each extra edge costs ½CV² like any other. With real gate delays your multiplier tree makes 1,871 physical toggles per random multiply-add against 1,244 at zero delay, about 1.4× the energy.
model.json idle law, as quoted in E66's registration; Q124's chip-diagram facts (glitches). No single file splits the card's watts among these, so there is no share bar for the card.Short circuit and leakage are current that never charges a node; a glitch is a real flip that nobody needed. At 0.517 V the first is small because the band of input voltage where both transistors conduct is narrower than at 0.7 V, which is why it can't explain why one flip costs more than another on this chip.
4Inside the multiply-add: one input bit sets off hundreds of flips
One flipped bit of b toggles 381 wires in the multiplier, and each wire pays ½CV²
Your Q124 flip, followed through one lane: bit 11 of b, with a = π, in a gate-level simulation of a netlist synthesized from the chip's RTL.
One bit of b flips. In this multiplier b is the multiplicand; a is the one that gets recoded.
Booth rows. Radix-4 Booth recoding reads a's significand three bits at a time and makes 16 rows of 33 bits, each 0, ±b or ±2b. The flipped bit of b changes a bit in every row that isn't zero. With a = π about half the rows are nonzero (9 of 16 by the recoding rule); with a = 1.0 only one or two are, one reason your quiet partner is cheaper.
Wallace tree. Four levels of 4:2 compressors, two full adders each, squeeze the 16 rows to two. A full adder's sum is a ⊕ b ⊕ c and its carry is the majority of the three, so a changed input always flips the sum and sometimes the carry, which moves one column left. On silicon: 248 full-adder cells, mostly the textbook 28-transistor mirror adder, plus XOR, majority and compound gates.
Product adder. Adds the last two rows; a change can ripple along the carry chain.
The rest of the seven-stage unit. Alignment, normalization, rounding and the accumulator see the changed product too.
Adding it up (estimates, arithmetic shown). 381 wires × 0.2985 fJ (the average net's ½CV²) ≈ 0.11 pJ. Priced from the actual cells: 0.11–0.13 pJ at zero delay, and glitches add about 40%. Against the card's 745 fJ, the multiplier's own switching is 0.11–0.13 ÷ 0.745 = 15–17% of this flip, 21–24% with glitches.
Your ladder's average flip (a = 1.0) costs 116.7 fJ at the board, 87.5 fJ on the minion rail (E60). The open netlist prices the same flips at 46.3 fJ: 32.9 fJ of net switching, 32.9 ÷ 0.2985 ≈ 110 average-net toggles, plus 13.4 fJ inside the cells. That's 53% of the rail.
Against one XOR: a register-file bit into one XOR costs 20.8 fJ (E60), and the XOR itself is a few percent of it (E61): most is the bit's trip from the register file. The multiply-add input bit costs 116.7 ÷ 20.8 = 5.6× more because one bit fans out into hundreds of nodes.
Over a whole random multiply-add, charge onto transistor gates is 0.31 of the card's 5.78 pJ
tensorfma32.json; Q126 open netlist; Q128 §2–3; E60; E61; E65.I started with the inverter because it's the simplest whole CMOS gate: one pull-up, one pull-down, one output node. The multiply-add's reduction tree is built from full adders instead, but every node in them is the same kind of node, charged through a pull-up network and drained through a pull-down, so each flip costs ½CV² exactly as in section 2. The multiply-add simply has hundreds of such nodes per flipped bit, and four fifths of each node's capacitance is wire.
5Scale: from Landauer's floor to the card's watts
A flipped multiply-add bit sits 37 million times above Landauer's floor; the card's second, 22 powers of ten
Each bar's length is the number of factors of ten above kT ln 2 at 58 °C (3.17 zJ), the die temperature your E60 and E65 runs launched at.
Read the bottom of the ladder as two factors, as your Q128 ledger does: one electron crossing the 0.517 V rail already leaves 26 times the floor, and the smallest transistor's gate takes 108 electrons per rise. Everything above is more of the same: more fins per net, wire that is four fifths of each net, hundreds of nets per flipped bit, about 4,100 net toggles per multiply-add, and 4.6 trillion multiply-adds a second at 9.18 TFLOPS.
6Could it be less?
Your read-port price follows V², not the clock
E60's ½CV² test: the read-port price on the minion rail on two 800 MHz cards, against aifoundry3 at 600 MHz and 0.522 V.
reduce.txt): aifoundry1’s card 0 at 0.604 V reads 1.384 against a V² of 1.339, and aifoundry2 at 0.617 V reads 1.426 against 1.400. A price that also grew with the clock (800 against 600 MHz) would sit near 1.79 and 1.87, the hollow circles.- Lower the voltage. Heat per flip goes as V²: aifoundry2's 0.617 V costs 1.43× aifoundry3's 0.522 V, so the lower rail saves 30% per flip. The limit: below threshold a transistor's current falls at most tenfold per 60 mV of gate voltage at room temperature (kT/q · ln 10), so as V drops, the off current grows against the on current and switching slows.
- Charge slowly, with a ramped supply. If the supply rises with the node over a time T much longer than RC, the loss drops to about (RC/T) · CV², and the stored half can be pulled back into the supply (adiabatic charging). A slow input edge on a fixed supply doesn't do this: your SPICE sweep shows it costs more, 7.5% at a 2 ns edge.
- Reversible logic. Landauer's kT ln 2 is the least heat for erasing one bit; logic that erases nothing could, in principle, go below it per step if run adiabatically. Today's smallest switch draws 8.94 aJ per rise, 2,755× the floor at 66 °C: 25.5× from the rail voltage, times 108 electrons from the gate's size. Neither factor is a thermodynamic limit; both are design.
7Inverter in depth: a tutorial from zero
The long way through section 2, for someone who knows programs and Boolean logic but no electronics. Twelve steps, each with a picture or a demo you can drive. The demos use this page's own numbers (0.517 V, the 2.233 fF average net, the 23.4 ps edge, all from Q128) unless a figure says it is illustrative.
1NOT is a function; in a chip, a bit is a voltage
In code, out = !in. In hardware there are no booleans, only wires, and a wire holds a voltage. A chip agrees on two levels: 0 V (ground) means 0, and the supply voltage, called VDD, means 1. On the ET-SoC-1's minion rail VDD is 0.517 V. An inverter is a circuit whose output sits at the opposite level from its input: it connects the output to VDD when the input is low, and to ground when the input is high.
The inverter's whole job, as a symbol and a table
Tap the button. The triangle means "drive"; the small circle on its tip means "invert".
| in | out |
|---|---|
| 0 (0 V) | 1 (0.517 V) |
| 1 (0.517 V) | 0 (0 V) |
2A short history: each new switch fixed the last one's problem
The inverter has been rebuilt from a better switch five times. Watch two problems get solved along the way: speed (moving parts, then hot glass) and power wasted while nothing happens.
From a clicking relay to 24 billion transistors
- 1830sThe relay. An electromagnet pulls a metal contact. A "normally closed" contact opens when the coil is powered: that is a NOT. Telephone exchanges ran on relays, and in his 1937 master's thesis Claude Shannon showed that relay circuits compute Boolean algebra. Slow (milliseconds), and the contacts wear out.
- 1904–06The vacuum tube. John Ambrose Fleming's valve (1904), then Lee de Forest's Audion (1906), in which a voltage on a wire grid controls a current through a vacuum. No moving parts, so thousands of times faster than a relay; one tube plus a resistor to the supply makes an inverter. ENIAC (1945) used about 17,500 tubes, which ran hot and burned out.
- 1925The field-effect idea. Julius Lilienfeld patents a switch in which a voltage on a plate controls the current in a solid. Nobody could make materials pure enough to build it for three decades.
- 1947The transistor. John Bardeen and Walter Brattain's point-contact transistor at Bell Labs, then William Shockley's junction transistor (1948). Small, cool and reliable.
- 1958–59The integrated circuit. Jack Kilby (Texas Instruments) and Robert Noyce (Fairchild) put several transistors and resistors on one piece of silicon. The Apollo Guidance Computer was later built from chips that each held two 3-input NOR gates.
- 1959The MOSFET. Mohamed Atalla and Dawon Kahng at Bell Labs build Lilienfeld's idea: a gate on a thin layer of oxide switching a channel in silicon. It is the switch of step 6, and of every modern chip.
- 1963CMOS. Frank Wanlass and Chih-Tang Sah at Fairchild pair an n-type and a p-type MOSFET so that one is always off, and the gate draws almost no current while it holds a value (step 7). RCA sold the first CMOS logic chips, the CD4000 series, in 1968; watches and calculators wanted the low power.
- 1970sNMOS microprocessors. Chips like the Intel 8080 and the MOS 6502 used only n-type transistors, with a load in place of the p-type one. Denser and faster at the time, but every gate with a low output draws current all the time.
- 1974Dennard scaling. Robert Dennard's rule: shrink every dimension and the voltage together, and the power per square millimetre stays flat. It held until the mid-2000s, when voltage stopped falling. Since then power, not transistor count, sets the limit, which is why your ladder counts flips.
- 1980sCMOS wins. As chips reached hundreds of thousands of gates, NMOS's idle current became the limit, and CMOS took over nearly all digital logic.
- 2011FinFETs. At 22 nm the channel stands up as a thin fin and the gate wraps it on three sides, so it can still shut the channel off at tiny sizes.
- TodayYour chip. The ET-SoC-1 is a 7 nm FinFET design of about 24 billion transistors, most of them in pairs doing what this section describes.
3Electricity in five ideas
You need five quantities. Each has a programmer's analogy and one number on this chip.
Charge, Q
An amount of electrons, in coulombs. One electron carries 1.602 × 10⁻¹⁹ C, so a coulomb is 6.24 × 10¹⁸ electrons. Think: the number of items in a queue.
Voltage, V
Energy per unit of charge: 1 volt is 1 joule per coulomb. It works like height: charge "falling" through 0.517 V gives up 0.517 × 1.602 × 10⁻¹⁹ = 8.28 × 10⁻²⁰ J per electron. A voltage is always between two points; "the node is at 0.3 V" means 0.3 V above ground.
Current, I
Charge per second, in amperes; 1 A is 6.24 × 10¹⁸ electrons a second. Think: throughput. By convention current flows from + to −; electrons, being negative, move the other way (section 1 draws both).
Resistance, R
How hard a path is to push charge through. Ohm's law: V = I × R. Charge forced through a resistance turns energy into heat, at the rate I²R. A switched-on transistor behaves roughly like a resistor.
Capacitance, C
How much charge a node holds per volt: Q = C × V, in farads. Every wire and every transistor gate is a tiny capacitor; your average net is 2.233 fF (femtofarads, 10⁻¹⁵ F). Think: a bucket whose water level is the voltage.
The one sentence to keep: a logic gate does not send bits down a wire; it fills or empties the small capacitor that the wire is, through a switch that behaves like a resistor. Everything below follows from it.
4The water picture of an inverter
Two valves and a bucket: one valve fills it from the tank, the other empties it to the drain
Tap to flip the input. Exactly one valve is open at a time; the water level is the output voltage.
5The capacitor: what a 1 costs
Filling the node takes Q = CV of charge; the supply pays CV², the node keeps ½CV²
Drag the sliders. The defaults are your average net on the minion rail.
6The transistor: a switch worked by a voltage
A MOSFET has three terminals that matter: source, drain and gate. The gate sits on a layer of insulating oxide a few atoms thick, so no current flows into it; it acts on the silicon below only through its electric field, like one plate of a capacitor. In an n-type MOSFET (NMOS), a positive gate voltage pulls electrons up under the oxide until they form a thin conducting channel joining source and drain. Below a threshold voltage (a few tenths of a volt in modern chips) there is no channel and the switch is off; above it the channel conducts, like a resistor that gets smaller as the gate rises.
Raise the gate and a channel of electrons appears between source and drain
An NMOS transistor in cross-section. The 0.2 V threshold here is illustrative.
Off: below the threshold there is no channel, only a tiny leakage current.
In 3D: a FinFET, the gate straddling the fin on three sides
The shape your card actually uses. Drag the model to turn it; the far side of the gate is drawn and the near side is cut away so the fin and the channel stay visible. The slider above drives both views.
NMOS: on when the gate is high
PMOS: on when the gate is low
7Two ways to build NOT, and why the second won
Design A, a switch and a resistor (resistor-transistor logic, and in spirit 1970s NMOS): a resistor ties the output up to the supply, and one NMOS can pull it down to ground. Input low: the switch is open and the resistor holds the output high. Input high: the switch closes and pulls the output low, but now current runs from the supply through the resistor and the switch to ground for as long as the input stays high, doing nothing useful. Design B, CMOS, replaces the resistor with a PMOS whose gate is tied to the same input. The two switches always disagree, one on and the other off, so there is never a standing path from the supply to ground; current flows only while the output changes.
Design A burns current whenever its output is low; CMOS only while it switches
Flip the input and see which design carries current while the gate sits still. Dark = switch on.
8The CMOS inverter, slowly: sweep the input from 0 to 0.517 V
Real inputs don't jump, they ramp. Drag the input slowly and watch three things: how strongly each transistor conducts, where the output sits, and the current that runs straight through both while both are partly on. That current is the short-circuit current of section 3; in a sharp edge it lasts only a few picoseconds.
The output stays high, then drops steeply in the middle; current runs straight through only near the middle
Curve shapes and the 0.2 V thresholds are illustrative, not measured on this chip.
Input low: the PMOS is on and the NMOS off, so the output is tied to the supply.
9Why digital works: each inverter cleans the signal
Analog signals degrade as they pass through stages; digital ones get cleaner. The reason is the curve of step 8: near either end its slope is shallow, so an input that is a bit off still gives an output very close to the rail. Pass a sloppy level through a few inverters and it snaps to a clean 0 or 1. Only an input right in the middle stays undecided for long, which is why designers keep signals out of that region.
A noisy input snaps to a clean rail within a few stages
Set a messy input. Each bar is the voltage after one more inverter (the illustrative curve of step 8).
10Speed: the output fills through a resistor
An on transistor is roughly a resistor R and the output node is a capacitor C, so the output follows a capacitor charging through a resistor: v(t) = V(1 − e−t/RC). The product RC, the time constant, sets the speed: the output reaches half the supply after 0.69 RC (the propagation delay) and goes from 20% to 80% in 1.39 RC. From Q128's 23.4 ps rise on the 2.233 fF average net, RC ≈ 16.9 ps, so the pull-up acts like about 7.6 kΩ.
More load is slower, a wider transistor is faster, and the heat per edge doesn't depend on R
Load multiplies C (more gates and wire to fill); drive strength divides R (a wider transistor). Derived from Q128's 23.4 ps edge.
11Power: flips per second times energy per flip
Each edge leaves ½CV² of heat. A node that switches τ times per clock cycle at clock frequency f therefore dissipates P = τ × f × ½CV². Summed over every node in the chip, this is the "dynamic power" of textbooks (usually written αCV²f, with α the fraction of cycles in which the node rises). It is why a program's data shows up in the power bill: the data decides how many nodes flip, which is what your Hamming ladder controls.
One net's power, and what a crowd of them costs
Defaults: your average net, the minion rail, 600 MHz (E60's clock on aifoundry3).
12From one inverter to a computer
Swap the single PMOS and NMOS for small networks and you get every other gate. NAND: two NMOS in series to ground (the output falls only if both inputs are 1) and two PMOS in parallel to the supply. NOR is the reverse. NAND alone can build any logic, so a chip is, to first order, many copies of the inverter's idea: a pull-up network and a pull-down network that never conduct at the same time.
An odd ring of inverters can never settle, so it oscillates
Each step is one gate delay. Highlighted nodes have an input that disagrees with what they show, so they flip next.
A ring of 3 repeats every 6 gate delays.
Two inverters in a loop hold a bit
Glossary
- VDD
- the supply voltage; a 1
- node
- a wire and everything on it; a capacitor
- threshold
- the gate voltage at which a channel forms
- fan-out
- how many gate inputs one output drives
- delay
- time for the output to cross half the supply
- leakage
- the small current through an off switch
← Back to section 2, the inverter animated electron by electron. History: Shannon's 1937 thesis; Atalla and Kahng (1959); Wanlass and Sah, ISSCC 1963; Dennard et al., IEEE JSSC 1974. Device physics: Rabaey, ch. 3 and 5; Weste and Harris, ch. 2.
Sources
Conventions: energies at 0.517 V (the open flow's minion rail) unless marked; an edge or toggle leaves ½CV² of heat; a rise draws CV² from the supply and a fall draws nothing; electrons are charge ÷ e. SPICE: ASAP7's TT corner at 25 °C.
- Q128, the transistor ledger (one device, the inverter by load, the edge sweep, leakage, nets, the bottom-up ledger, Landauer): lab repo, 2026-10-27-transistor-ledger; the page From matmul speed to one transistor switch.
- Q126: ASAP7, one switch in SPICE; the open netlist; the toggle recount.
- Q124, the multiply-add as built (Booth rows, full adders, the 381 wires, glitches):
tensorfma32.json; the page TensorFMA32 as built, flow M. - E60, the Hamming ladder (116.7 fJ, 20.8 fJ, the V² test):
reduce.txt; What one flipped bit costs on the ET-SoC-1. E61: the one-gate runs. E65: bit prices and the flow-M flip. E66: the idle law under test. - 21 Sep, the Horace experiment:
horace3.txt(38.29 W on zeros, 63.40 W on random data at 9.18 TFLOPS). - Physics: J. Rabaey, A. Chandrakasan, B. Nikolić, Digital Integrated Circuits, 2nd ed., ch. 5 (the inverter's dynamic, short-circuit and static power); N. Weste, D. Harris, CMOS VLSI Design, 4th ed., ch. 5 (power); E. Pop, S. Sinha, K. Goodson, “Heat generation and transport in nanometer-scale transistors,” Proc. IEEE 94, 1587 (2006); R. Landauer, IBM J. Res. Dev. 5, 183 (1961); C. Bennett, IBM J. Res. Dev. 17, 525 (1973); W. Athas et al., “Low-power digital systems based on adiabatic-switching principles,” IEEE Trans. VLSI Syst. 2, 398 (1994).